1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device comprising a redundancy circuit for saving a faulty memory cell.
2. Description of the Related Art
In a semiconductor memory device, in the case where a faulty memory cell has been detected, there is adopted a redundancy circuit system (redundancy system) in which the faulty memory cell is replaced with a redundancy cell, that is, a redundancy cell is used in place of a faulty memory cell, thereby improving the yield of the semiconductor storage device. Currently, in a generally employed redundancy system, one or plural rows of memory cell arrays or one or plural columns are defined as a replacement unit (namely, a saving unit). The replacement unit of memory cells including a faulty memory cell, in a sub-block called a saving block unit for saving such faulty memory cells is replaced with a redundancy saving unit (spare element) having the same size. In the case where a faulty sub-block containing such faulty memory cell has been detected, a spare element is used in place of such faulty cell block.
In order to store an address information of a replacement unit containing a faulty memory cell, it is required to employ a nonvolatile storage element. Currently, a fuse is generally used. Address information is generally composed of a plurality of bits, and thus, a fuse set of plural fuses that correspond to such plurality of bits becomes a unit of storage of address information on one sub-block. In general, the number of spare elements corresponds to that of fuse sets one by one, and thus, the fuse sets whose number is the same as that of spare elements are arranged in a memory chip. In the case of using such spare element, the fuse in the fuse sets that correspond to the spare elements is disconnected according to address information on a faulty cell. This system is simple in configuration, and is currently widely used.
In a semiconductor memory, memory cells are arranged in a planar (two dimensional) manner. Currently, it is well known to store xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d bit information in one memory cell. As address information for designating one memory cell, there are used two addresses, row address and column address. That is, two coordinates, i.e., an X-coordinate (row address) and a Y-coordinate (column address) are used in order to designate one memory cell. In order to save a faulty memory cell, two circuits, i.e., a row redundancy circuit and a column redundancy circuit are mounted so as to use any of a method for saving the faulty memory cell with a row spare element and a method for saving the faulty memory cell with a column spare element. However, the number of faults that can be saved with the row spare element is independent of the number of faults that can be saved with the column spare element.
As described above, a redundancy system requires a redundancy circuit such as spare element and fuse set. In a conventional redundancy system in which the spare element corresponds to the fuse set in number one by one, the number of fuse sets increases with an increased number of spare elements, and a memory chip area also increases. In this case, the fuse set generally requires a larger area than the spare element, and thus, the area efficiency of the redundancy circuit is significantly lowered.
In order to solve this problem, there are proposed a variety of redundancy systems that improve the area efficiency of the redundancy circuit. For example, there is known a flexible redundancy system (refer to xe2x80x9cFault-Tolerant Design for 256 Mb DRAMxe2x80x9d (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, No. 4, April 1996) proposed by Kirihata et al. for example. In this system, one spare element covers a wide cell array region. Thus, even in the case where faulty cells locally, i.e. collectively, exist at a portion of a memory chip, such faulty cells can be saved in a manner similar to a case in which faults are distributed uniformly in a cell array. Because of this, this system reduces the number of spare elements, whereby the area efficiency of the redundancy circuit can be improved. In addition, this system is effective in the case where the average number of faulty cells per memory chip is identified or can be predicted.
On the other hand, in recent years, there has been developed a memory chip on which a memory cell array is divided into a plurality of sections. For example, there is a memory chip having a plurality of banks, wherein these banks are activated at the same time. In such a memory chip, it is impossible to use a row spare element in a bank, for saving faulty memory cells in units of rows as a row spare element in another bank. Thus, a spare element is unavoidably provided for each bank. More banks increase the number of divisions in memory cell arrays in a memory chip, and thus, one spare element can cover only a small cell array area. Even in the case where the spare element can cover only such small cell array region or even in the case where faults locally exist at a portion of a memory cell array, the spare element must be provided for such each small cell array region in order to save faulty cells. Therefore, the total number of spare elements significantly increases, resulting in a significant increase in required memory chip area. That is, in view of the entire memory chip, the number of spare elements that significantly exceeds the average number of faulty cells per memory chip is incorporated in one memory chip, and thus, the area efficiency of the memory chip is degraded.
In addition, in a semiconductor memory device required to transfer a large amount of data at one time due to the pursuit of high speed, a column is divided in fine units. Thus, a column spare element for saving a faulty memory cell in units of columns is unavoidably provided for each column unit. Therefore, the area efficiency of the memory chip is significantly lowered.
In view of such a circumstance, there has been proposed a flexible mapping redundancy technique in which the number of fuse sets that exceeds the assumed number of faulty cells in the entire cell array is reduced to be smaller than the total number of spare elements in a semiconductor memory device disclosed in S. Takase et al., xe2x80x9cA 1.6-Gbyte/s DRAN with Flexible Mapping Redundancy Technique and Additional Refresh Schemexe2x80x9d IEEE JSSC, VOL 34, No. 11, pp. 1600-1605, November, 1999 and U.S. Pat. No. 6,188,618.
In the flexible mapping redundancy of the semiconductor memory device disclosed in U.S. Pat. No. 6,188,618, a plurality of spare elements for replacing faulty cells are arranged in a memory cell array contained in a memory chip. A fuse set contains a faulty address. The fuse set also contains mapping information indicating a correspondence between the fuse set and a spare element. In the case where a faulty address coincides with an input address, a signal for activating the corresponding spare element is outputted. There is no need to associate each fuse set with a spare element one by one.
Hereinafter, a flexible mapping redundancy technique disclosed in U.S. Pat. No. 6,188,618 will be briefly described with reference to matters related to the present invention.
In a memory cell array of the semiconductor memory device, a plurality of spare elements for saving faulty cells are disposed in a memory chip, and there are fuse sets fewer than the total number of spare elements. These fuse sets each contain a faulty address and mapping information indicating a correspondence between and the fuse set and the spare element. In the case where a faulty address coincides with an input address, an arrangement is provided so as to output a signal for activating the corresponding spare element.
FIG. 12 schematically shows a configuration of a fuse set that contains the mapping information. In a fuse set shown in FIG. 12, a fail address detector circuit (Fail Address Detector) 121 receives an address acquisition signal xe2x80x9cstrbxe2x80x9d. In the case where an input address (sometimes including address or bank address) coincides with a faulty element address, when the address acquisition signal xe2x80x9cstrbxe2x80x9d is activated after input address determination, an address match signal xe2x80x9cmatchxe2x80x9d is activated.
A spare element selector circuit (Spare Element Selector) 122 stores in advance information on which spare element is replaced by using this fuse set, by fuse, for example. When the address match signal xe2x80x9cmatchxe2x80x9d is activated, a spare hit signal xe2x80x9csprhitxe2x80x9d for selecting a spare element is outputted.
Now, a case in which the flexible mapping redundancy technique is applied to save a row will be described hereinafter. For clarity, as shown in FIG. 13, for example, assume that 8(=23) banks, i.e., bank 0 to bank 7 are arranged on a memory chip, and one bank is comprised of one cell array. However, the present invention is applicable even if one bank is comprised of a plurality of sub-cell arrays.
Assume that one bank has 512 normal word lines and 16 spare word lines, and that two word lines are units of replacement (spare elements).
In the case where a faulty element exists in a normal elements, such faulty element is replaced with a spare element, whereby a row saving is carried out.
In order to designate a faulty element, it must be specified as to which normal element is faulty, of 256 normal elements obtained by dividing the total number of word lines for one bank, 512 by the number of word lines in units of replacement, 2. When an address required for such designation is obtained, 8 bits are obtained from log (256)/log (2). On the other hand, it must be specified as to which spare element is used for replacement, of 8 spare elements obtained by dividing all of 16 spare word lines by the number of word lines in units of replacement, 2. When an address required for this designation, 3 bits are obtained from log (8)/log (2).
Therefore, it is required that each fuse set used for row saving contains a total of 15 fuses, one enable control fuse (Enable Fuse); eight faulty address designation fuses (Addresses for row decoders), three bank address designation fuses (Address for banks), and three bank spare element designation fuses (Selector for mapping spare row element within a bank).
FIG. 14 schematically shows a configuration of a fuse set used for row saving as described above.
Here, a fail address match detector 141 receives a row address acquisition signal xe2x80x9crstrbxe2x80x9d. In the case where a row address input xe2x80x9cAddress for row detectorsxe2x80x9d and a bank address input xe2x80x9cAddress for banksxe2x80x9d coincide with a faulty element address, an output signal, i.e., an address match signal xe2x80x9cmatchxe2x80x9d of the fail address match detector 141 is activated when the address acquisition signal xe2x80x9cstrbxe2x80x9d is activated after input address determination.
A decoder 142 for a spare row element selector circuit stores in advance information indicating which spare row element is used for faulty element replacement by this fuse set, for example, by fuse, xe2x80x9cSelector for mapping spare row element within a bankxe2x80x9d. When the address match signal xe2x80x9cmatchxe2x80x9d is activated, xe2x80x9crronxe2x80x9d (which denotes xe2x80x9crow redundancy onxe2x80x9d) and sra  less than 0:2 greater than  are outputted as spare hit signals for selecting a spare element.
FIG. 15 shows a wired OR circuit as an example of circuit for performing logical processing (wired OR) of a plurality of identical outputs for a plurality of fuse sets shown in FIG. 14.
In the figure, reference numeral 151 denotes a PMOS transistor in which a source is connected to a power supply node, a drain is connected to a wired OR output node, and a gate is supplied with a row precharge signal xe2x80x9crprchxe2x80x9d. Reference numeral 152 denotes a NMOS transistor in which a drain is connected to a wired OR output node, a source is connected to ground, and a gate is supplied with one bit of the signals xe2x80x9crronxe2x80x9d and sra  less than 0:2 greater than  of a corresponding fuse set.
Referring now to FIG. 14 and FIG. 15, a description will be given with respect to an operation for, in the case where inputted row address and row bank address correspond to a faulty element address, replacing such a faulty element with a spare element.
In this example, one memory chip has 8 banks, and each bank has 256 normal elements and spare elements 8. A total of 64 (8xc3x978) spare elements are provided.
In the case where an address programmed by a fuse in one fuse set coincides with an input address, a row redundancy signal xe2x80x9crronxe2x80x9d is activated, and a wired OR node signal xe2x80x9cbRRONxe2x80x9d is set to Low (xe2x80x9cLxe2x80x9d). In addition, a logic of a signal xe2x80x9csra  less than 0:2 greater than  is determined depending on information on mapping fuse of this fuse set, and further, a logic of a wired OR node signal xe2x80x9cbSRA  less than 0:2 greater than  is determined.
When the signal xe2x80x9cbRRONxe2x80x9d is set to xe2x80x9cLxe2x80x9d, a normal row decoder of a bank designated by the inputted bank address is deactivated. Then, any of eight spare elements contained in that bank is designated by 3 bits of the signal xe2x80x9cbSRA  less than 0:2 greater than , and is activated.
Now, a case in which the flexible mapping redundancy technique is applied to column saving will be described here.
For example, as shown in FIG. 16, assume that 8 banks, i.e., bank 0 to bank 7 are arranged on a memory chip, each bank is divided into 8 segments, i.e., seg 0 to seg 7 in a column direction, and 4-bit data (the number of bits are arbitrarily set) is outputted from such each segment.
Each segment has 64 normal column selection lines xe2x80x9cnormal CSLxe2x80x9d. In each column cycle, one of 64 normal column selection lines xe2x80x9cnormal CSLxe2x80x9d in each segment is activated.
Further, assume that each segment has 2 spare column selection lines xe2x80x9cspare CSLxe2x80x9d, and a replacement element in each column is one column selection line. In the case where a replacement element (that is, one normal column selection line xe2x80x9cnormal CSLxe2x80x9d) is faulty, this faulty element is replaced with one spare element (i.e., spare column selection line xe2x80x9cspare CSLxe2x80x9d), whereby column saving is carried out.
Here, let us consider a case in which one normal element is faulty, and the replacement of the faulty element is made in the segment containing the faulty element. That is, let it be considered a case where one normal element is faulty, and it is needed that the faulty element is replaced with one of the two spare column select lines arranged in the segment containing the faulty element. It is required that each fuse set used for column saving contains a total of 14 fuses, one enable control fuse (Enable Fuse), six faulty address designation fuses (Address for column select line), three bank address designation fuses (Address for banks), three segment designation fuses (segment select), and one segment spare address designation fuses (Selector for mapping spare column element within each segment).
FIG. 17 schematically shows a configuration of a fuse set used for column saving as described above.
FIG. 18 shows a wired OR circuit as an example of circuit for performing logic processing of identical outputs of a plurality of fuse sets shown in FIG. 17.
In the figures, reference numeral 181 denotes a PMOS transistor in which a source is connected to a power supply node, a drain is connected to a wired OR output node, and a gate is supplied with a column precharge signal xe2x80x9ccprchxe2x80x9d. Reference 182 denotes a NMOS transistor in which a drain is connected to a wired OR output node, a source is connected to ground, and a gate is supplied with one bit of chit  less than 0:15 greater than  from a corresponding fuse set.
Referring now to FIG. 17 and FIG. 18, a description will be given with respect to an operation for, in the case where an inputted address corresponds to a faulty element address, replacing such faulty element with a spare element.
In this example, one memory chip has eight segments, one segment has two spare elements, and there exist a total of 16 (8xc3x972) spare elements. In the case where an inputted column address and a column bank address correspond to a faulty element, such faulty element must be replaced with a spare element.
In the case where an address programmed address by a fuse in one fuse set coincides with an input address, column redundancy is used. Based on information on a 4-bit mapping fuse contained in this fuse set, only one of the signals xe2x80x9cchit  less than 0:15 greater than  is activated, and further, any one of the wired OR node signals xe2x80x9cbSCSLE  less than 0:15 greater than  is set to xe2x80x9cLxe2x80x9d. This signal xe2x80x9cbSCSLE  less than 0:15 greater than corresponds to 16 spare elements, and determines which spare column selection lines xe2x80x9cspare CSL  less than 0:15 greater than  is activated.
Of course, address match may be obtained in different fuse sets in the same column cycle. However, in that case, it is assumed that, although a plurality of signals xe2x80x9cbSCSLE  less than 0:15 greater than  are set to xe2x80x9cLxe2x80x9d, a normal column selection line xe2x80x9cnormal CSLxe2x80x9d is permitted as long as the line is replaced with a spare column selection line xe2x80x9cspare CSLxe2x80x9d within the same segment as the faulty xe2x80x9cnormal CSLxe2x80x9d. However, this assumption is not essential.
For example, when one signal xe2x80x9cbSCSLExe2x80x9d is set to xe2x80x9cLxe2x80x9d, the normal column decoder of the corresponding segment is deactivated. Then, activation of the normal; column selection line xe2x80x9cnormal CSLxe2x80x9d is restricted, and either one of the two spare column selection lines xe2x80x9cspare CSLxe2x80x9d in that segment is activated.
In the meantime, in the semiconductor memory device disclosed in U.S. Pat. No. 6,188,618 as described above, in the case where each fuse set is applied for column saving, the maximum number enabling column saving is determined depending on the number of column fuse sets. In the case where each fuse set is applied for row saving, the maximum number enabling row saving is determined depending on the number of row fuse sets.
In the above fuse sets, conventionally, a fuse set used for row saving, and configuring a portion of a row redundancy circuit, is independent of a fuse set used for column saving, and configuring a portion of a column redundancy circuit. Thus, the number of faults enabling row saving has been independent of the number of faults enabling column saving. For example, in one memory chip, if a number of faults occur in one row, in general, such faults are handled as row faults, and row saving is carried out. If a number of faults occur in one column, in general, such faults are handled as column faults, column saving is carried out.
However, in a memory chip, the number of row faults or the number of column faults greatly depends on process, lot, wafer, or memory chip. For example, in the case where row faults are large in number, and column faults are small in number, the number of faults that can be replaced is restricted depending on the number of fuse sets for row saving. Even if an unused fuse remains in a fuse set for column saving, it has been impossible to apply this fuse to row saving. That is, there has been a problem that the degree of freedom for replacement is small, and the yields of the device are degrated.
As described above, in a conventional semiconductor memory device having a fuse set to which a flexible mapping redundancy technique is applied, a fuse set applied to row saving is independent of a fuse set applied to column set. Thus, there has been a problem that the degree of freedom for replacement is small, and the yields of the device are degraded.
The present invention has been made in order to solve the foregoing disadvantage. It is an object of the present invention to provide a semiconductor memory device capable of achieving high replacement efficiency and high degree of freedom for replacement with a small area by applying a flexible mapping redundancy technique and sharing a storage element and a redundancy circuit for row saving and a storage element and a redundancy circuit for column saving, the semiconductor memory device comprising a redundancy system capable of contributing to improvement of yields.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, the memory cell array being divided into a plurality of sub-cell arrays; a row redundancy element and a column redundancy element disposed in correspondence to each of the sub-cell arrays; a normal row decoder for selecting a row of the memory cell array according to an input address; a normal column decoder for selecting a column of the memory cell array according to an input address; a plurality of information storing circuits each storing an address of a faulty memory cell contained in each memory cell array and storing mapping information indicating a correspondence between the each storing circuit and the row redundancy element or a correspondence between the each storing circuit and the column redundancy element, the information storing circuits being adopted to output a row saving control signal for replacing the faulty memory cell with the row redundancy element or a column saving control signal for replacing the faulty memory cell with the column redundancy element based on the mapping information and a match result in the case where the address of the faulty memory cell coincides with an input address; a control circuit for deactivating the normal row decoder according to the row saving control signal supplied from the information storing circuit; a spare row decoder activated according to the row saving control signal supplied from the information storing circuit, the spare row decoder selecting the row redundancy element; a control circuit for deactivating the normal column decoder according to the column saving control signal supplied from the information storing circuit; and a spare column decoder activated according to the column saving control signal supplied from the information storing circuit, the spare column decoder selecting the column redundancy element, wherein at least one of the plurality of information storing circuits is a row/column common information storing circuit that contains a first nonvolatile storage element capable of programming information on whether row saving or column saving is carried out by using the information storing circuit, and that is selectable for use in either one of the row saving and column saving.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, the memory cell array being divided into a plurality of sub-cell arrays; a row redundancy element and a column redundancy element disposed in correspondence to each of the sub-cell array, and a plurality of information storing circuits each storing an address of a faulty memory cell contained in each memory cell array and storing mapping information indicating a correspondence between the each storing circuit and the row redundancy element or a correspondence between the each storing circuit and the column redundancy element, the information storing circuits being adopted to output a row saving control signal for replacing the faulty memory cell with the row redundancy element or a column saving control signal for replacing the faulty memory cell with the column redundancy element based on the match result and the mapping information in the case where the address of the faulty memory cell coincides with an input address; wherein at least one of the plurality of information storing circuits is a row/column common information storing circuit that contains a first nonvolatile storage element capable of programming information on whether row saving or column saving is carried out by using the information storing circuit, and that is selectable for use in either one of the row saving and column saving.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.